The present invention relates generally to memory systems and more particularly to apparatus and methodologies for verifying soft programming in semiconductor memory devices.
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. More recently, dual bit memory cell architectures have been introduced, wherein each cell can store two bits of data. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells typically include a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained in the form of electrical charge. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell. In an erase or program operation the voltages are applied so as to cause a change in charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 10MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. In such single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a wordline associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bitline. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bitline. In addition, each flash cell associated with a given bit line has its stacked gate terminal coupled to a different wordline, while all the flash cells in the array have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Programming a flash memory cell is typically done by channel hot electron (CHE) by grounding the source region, applying a relatively high positive voltage to the control gate and applying a moderate voltage to the drain to generate high energy or hot electrons, which accumulate in the floating gate until the effective threshold voltage of the cell rises to a programmed threshold voltage, which is sufficient to inhibit current flow through the channel region during any subsequent read mode operation. Typically, in the read mode, a relatively low positive voltage is applied to the drain, a moderate voltage is applied to the control gate and the source is grounded. The magnitude of the resulting current can be sensed in order to ascertain whether the cell is programmed or erased.
Erasing flash cells is done using Fowler-Nordheim tunneling between the floating gate and the source (e.g., source erase or negative gate erase) or between the floating gate and the substrate (e.g., channel erase). In a source erase operation, a high positive voltage (e.g., approximately 12V) is provided to the source, the gate and the substrate are grounded, and the drain is floated. Negative gate erase operation involves providing a moderate positive voltage (e.g., 5V or VCC) to the source, floating the drain, grounding the substrate, and applying a negative voltage (e.g., xe2x88x9210V) to the gate. Channel erase operation involves applying a high positive voltage to the substrate and grounding the gate, while the source and drain are floated.
When a sector of memory cells is erased, an erase verify operation is subsequently performed to ensure proper erasure of each of the cells in the sector. Thereafter, soft programming is employed, wherein a small amount of charge is injected into the cell to rectify or mitigate over-erased conditions resulting from repeated erasure of the cell. The amount of charge injected during the soft programming is controlled so as not to overprogram the cell, so that it passes erase verify even after a soft program verify operation, which is performed right after the soft programming operation.
During soft program verify operations, a positive voltage is provided to the gate terminal of the cell by an internally generated voltage source in the memory device. However, if such a voltage source provides an unstable gate voltage, or where the voltage level is too high (e.g., due to overshoot), anomalous soft program verify results may be obtained. For example, improperly erased or over-erased cells may be identified as good, and/or properly erased cells may be identified as bad. As memory device densities continue to increase, providing dedicated voltage sources for the various cell terminals (e.g., gate, drain, source, etc.) for each operation (e.g., read, write, erase, soft program verification, etc.) is difficult and may not be cost effective. However, the impedance characteristics of the various terminals during such operations makes it difficult to apply a single voltage source to such varied tasks. Thus, there is a need for methodologies and apparatus by which voltage sources may be employed for different cell terminals during different operations, while mitigating or avoiding anomalous results associated with high or unstable soft program verify gate voltage levels.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention relates to methods and apparatus for verifying soft programming of one or more cells in a memory device, which allow the use of a drain pump or other voltage source in applying a gate voltage during soft program verification. The invention finds application in association with single-bit (e.g., stacked gate) as well as dual bit memory cell architectures. In one aspect of the invention, methods comprise providing a voltage source to a core cell gate, and verifying soft programming after an overshoot in the regulated voltage source has settled, whereby adverse effects associated with a high or unstable gate voltage can be mitigated or avoided. This technique can be employed to allow use of many different voltage source types found in flash and other memory devices (e.g., single stage pump circuits, multi-stage pumps, etc.) to provide voltage to a cell gate during a soft program verification or other operations, even where such voltage sources suffer from initial overshoot or instability.
Another aspect of the invention provides memory devices having a logic circuit providing a regulated voltage source to the core cell gate during a soft program verify operation, and a sensor to verify soft programming of the cell when a first voltage (e.g., about 2.7 volts) is applied to the gate from the regulated voltage source. In order to ensure proper verification of the soft programming, the logic circuit provides a soft program verify signal to the sensor to verify soft programming after an overshoot in the voltage source has settled, such as by waiting a fixed time period after the voltage source initially rises to a regulation value (e.g., about 4 volts in one implementation). For example, a delay or wait time may be established by the logic circuit after the voltage source""s initial rise to a regulation level, to allow the regulation to reduce (e.g., settle) any intervening overshoot, by which a stable gate voltage of proper level is applied at the time when the verify is performed.
The invention thus allows use of a variety of voltage sources, such as a drain pump, in providing the gate voltage during soft program verify operations. For example, where the drain pump is alternatively used for connection to the drain during programming, such pump may be capable of supplying a relatively large amount of current (e.g., 2 mA). Although the soft program verify operation uses the resistor divided voltages from the drain pump to the gate of the core cell and the gate of the reference cell, which might result in gate voltage overshoot, the invention advantageously waits to perform the soft program verify until such overshoot has subsided. This may be accomplished using a logic circuit or system verifying that the cell is currently in a soft program verify mode, and that the voltage source (e.g., the drain pump) level has risen above the regulation level (e.g., about 4 volts). Thereafter, the logic circuit delays the provision of a soft program verify signal to the associated sensor, for example, by a fixed time period (e.g., about 200 ns or more and about 500 ns or less, such as about 400 ns).
This wait period can be implemented using timers, or other circuitry, whereby proper soft program verification is facilitated.
Another aspect of the invention provides methodologies for verifying soft programming in a memory device, wherein a regulated voltage source is provided to the cell gate through a voltage divider during a soft program verify operation, and soft programming of the core cell is verified using a sensor after overshoot in the regulated voltage source has settled. The verification may comprise waiting a fixed time period (e.g., about 400 ns) after the voltage source is greater than a certain voltage, such as a regulation value (e.g., about 4 volts in one implementation), and sensing a current associated with the cell after the fixed time period using a sensor.
The wait period can be implemented by creating a first signal when the regulated voltage source has a value greater than a second voltage using a first circuit, generating a first wait signal indicative of a fixed time period according to the first signal using a second circuit, providing a second wait signal a fixed time period after the first signal using a timer circuit, and providing a soft program verify signal to the sensor according to the second wait signal using a state machine. The invention thus provides flexibility in the design of memory circuits, by which voltage sources suffering from overshoot problems can successfully be employed in providing soft program verify gate voltages.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.